The escalating demands for high density and performance associated with non-volatile memory devices, such as electrically erasable programmable read only memory (EEPROM) devices, require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology.
One particular problem with scaling memory devices to reduce their size is that the memory devices often exhibit degraded performance. For example, reducing the size of various conductive structures in the memory devices, such as bit lines, often results in increased resistance associated with the bit lines. This increased resistance may require an increase in the voltage to program and/or erase the memory cells in the memory device, which may cause additional problems. These problems may make it difficult for the memory device to be efficiently programmed and/or erased and, ultimately, may lead to device failure.